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(R)
VN710SP
AUTOMOTIVE GLOW PLUG DRIVER
PRELIMINARY DATA
TYPE VN710SP
s s s s s
RDS(on) 18m
IOUT 35 A
VCC 16 V
CMOS COMPATIBLE INPUT ON STATE OPEN LOAD DETECTION OFF STATE OPENLOAD DETECTION SHORTED LOAD PROTECTION UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN PROTECTION AGAINST LOSS OF GROUND VERY LOW STAND-BY CURRENT WHEN ENABLE PIN IS LOW REVERSE BATTERY PROTECTION (*)
10
1
s s
PowerSO-10TM
s
DESCRIPTION The VN710SP is a monolithic device made using STMicroelectronics VIPower M0-3 technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transients compatibility table). Active current limitation combined with thermal shutdown protect the device against BLOCK DIAGRAM
overload. After a thermal shutdown event, device stays latched off and diagnostic stays at a low level until next falling edge of input signal. The device detects open load condition both in on state and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. Enable pin allows to switch the device to idle state with very low quiescent current from VCC. When enable is low, device turns off regardless of input pin state.
V CC
VCC CLAMP GND
OVERVOLTAGE DETECTION UNDERVOLTAGE DETECTION Power CLAMP DRIVER
INPUT
LOGIC CURRENT LIMITER
OUTPUT
STATUS ENABLE
ON STATE OPENLOAD DETECTION OFF STATE OPENLOAD AND OUTPUT SHORTED TO VCC DETECTION OVERTEMPERATURE DETECTION
(*) See application schematic at page 7
October 2000
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VN710SP
THERMAL DATA
Symbol Rtj-case Rtj-amb (*) Parameter Thermal resistance junction-case Thermal resistance junction-ambient Value 1.4 52 Unit C/W C/W
(*) When mounted on a standard single-sided FR-4 board with 50mm2 of Cu (at least 35m thick).
ABSOLUTE MAXIMUM RATING
Symbol VCC -VCC -I GND IOUT -IOUT IIN Ien ISTAT VESD Ptot Tj Tc Tstg Parameter DC supply voltage Reverse DC supply voltage Reverse DC ground pin current DC output current Reverse DC output current DC input current DC enable current DC status current Electrostatic discharge (R=1.5k; C=100pF) Power dissipation at Tc=25C Junction operating temperature Case operating temperature Storage temperature Value 41 -0.3 -200 Internally limited -35 +/-10 +/-10 +/-10 2000 89 Internally limited -40 to 150 -55 to 150 Unit V V mA A A mA mA mA V W C C C
CONNECTION DIAGRAM (TOP VIEW)
GROUND ENABLE STATUS INPUT N.C.
6 7 8 9 10 11 VCC
5 4 3 2 1
OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
CURRENT AND VOLTAGE CONVENTIONS
Ien Ven IIN VIN ISTAT STATUS GND VSTAT IGND OUTPUT ENABLE INPUT VCC
ICC VCC
IOUT VOUT
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ELECTRICAL CHARACTERISTICS (7VSymbol VCC VUSD VOV RON Parameter Operating supply voltage Undervoltage shutdown Overvoltage shutdown On state resistance IOUT=15A Off state; VCC=13V; Ven=VOUT=0V; VIN=5V IS Supply current Off state; VCC=13V; Ven=VOUT=0V; VIN=5V; Tj=25C On state; VCC=13V; VIN=0V; IOUT=0A; Ven>Venh ILGND IL(off1) IL(off2) Output current at Turn-off Off state output current Off state output current VCC=VGND=16V VIN=Ven=n.c.; VOUT=0V VOUT=0V; VIN>VIH VOUT=3.5V; VIN>VIH; Ven>Venh 0 -75 10 10 2.5 Test Conditions Min 5.5 3 16 Typ 13 4 18 Max 16 5.5 20 20 40 25 20 4 2 50 0 Unit V V V m m A A mA mA A A
IOUT=15A; Tj=25C
SWITCHING (VCC=13V)
Symbol td(on) td(off) dVOUT/ dt(on) dVOUT/ dt(off) Parameter Turn-on delay time Turn-off delay time Turn-on voltage slope Turn-off voltage slope Test Conditions RL=0.85, from VIN falling edge to VOUT=1.3V RL=0.85, from VIN rising edge to VOUT=11.7V RL=0.85, from VOUT=1.3V to VOUT=10.4V RL=0.85, from VOUT=11.7V to VOUT=1.3V Min Typ 40 80 0.1 0.1 Max Unit s s V/s V/s
INPUT PIN (active low)
Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input low level Low level input current Input high level High level input current Input hysteresis voltage Input clamp voltage IIN=1mA IIN=-1mA Test Conditions VIN=1.25V; Ven>Venh VIN=3.25V; Ven>Venh VIN=3.25V; Ven=0V -300 0.5 6 Min -35 3.25 -4 -4 6.8 -0.7 8 Typ Max 1.25 Unit V A V A A V V V
ENABLE PIN (active high)
Symbol Venl Ienl Venh Ienh Vehyst Vencl Parameter Test Conditions Enable low level Low level enable current Ven=1.25V Enable high level High level enable current Ven=3.25V Enable hysteresis voltage Ien=1mA Enable clamp voltage Ien=-1mA Min 4 3.25 35 0.5 6 6.8 -0.7 8 Typ Max 1.25 Unit V A V A V V V 3/11
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VN710SP
ELECTRICAL CHARACTERISTICS (continued) STATUS PIN (Open Drain)
Symbol VSTAT ILSTAT CSTAT VSCL Parameter Status low output voltage Status leakage current Status pin input capacitance Status clamp voltage Test Conditions ISTAT=1.6mA Normal operation; VSTAT=5V Normal operation; VSTAT=5V ISTAT=1mA ISTAT=-1mA 6 6.8 -0.7 Min Typ Max 0.5 10 100 8 Unit V A pF V V
PROTECTIONS
Symbol TTSD TR Thyst tSDL Ilim Vdemag Parameter Shut-down temperature Reset temperature Thermal hysteresis Overload detection delay Current limitation Turn-off output clamp voltage Test Conditions Min 170 135 7 35 IOUT=2A; VIN=5V; L=6mH Typ 190 15 55 20 80 Max Unit C C C s A V
Tj>TTSD
VCC-41 VCC-48 VCC-55
OPENLOAD DETECTION
Symbol IOL Parameter Openload on state detection threshold Test Conditions VIN=0V Min 0.1 1.5 Typ 1 2.5 Max 2 3.5 500 IOUT=0V 200 Unit A V s s
VOL tDOL(off) tDOL(on)
Openload off state voltage VIN=5V detection threshold Openload detection delay at turn-off Openload detection delay at turn-on
OPENLOAD STATUS TIMING (with external pull-up) IOUTVOL VIN VIN
OVERTEMP STATUS TIMING Tj>TTSD
VSTAT VSTAT
tDOL(off)
tDOL(on)
tSDL
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VN710SP
Switching Time Waveforms
VOUT 90% 80% dVOUT/dt(on) 10% t VIN td(on) td(off) dVOUT/dt(off)
t TRUTH TABLE
CONDITIONS ENABLE INPUT OUTPUT STATUS
Normal operation Current limitation Overtemperature Undervoltage Overvoltage Output voltage > VOL Output current < IOL Any
H H H H H H H H H H H H H H L
H L H L L H H L H L H L H L X
L H L X L (*) L L L L L H H L H L
H H H H L (*) L X X H H L H H L H
(*) Latched on first overtemperature event; latch cleared on next input falling edge.
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VN710SP
ELECTRICAL TRANSIENTS REQUIREMENTS ON VCC PIN
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 TEST LEVELS I -25V +25V -25V +25V -4V +26.5V II -50V +50V -50V +50V -5V +46.5V III -75V +75V -100V +75V -6V +66.5V IV -100V +100V -150V +100V -7V +86.5V Delays and Impedance 2ms, 10 0.2ms, 10 0.1ms, 50 0.1ms, 50 100ms, 0.01 400ms, 2
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5
TEST LEVELS RESULT I C C C C C C II C C C C C E III C C C C C E IV C C C C C E
CLASS C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
SUGGESTED SCHEME FOR ISO TEST PULSE
10K from test generator
10K
ENABLE INPUT
VCC
10K STATUS
OUTPUT GND
open
Warning: Input, Enable, Status Pulled to VCC voltage during negative transient.
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VN710SP
APPLICATION SCHEMATIC
+5V
+5V
VCC Rprot STATUS Dld C Rprot INPUT OUTPUT Rprot ENABLE GND
VGND
RGND
DGND
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggest to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
LOAD DUMP PROTECTION
Dld is necessary (Transil or MOV) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
C I/Os PROTECTION:
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot ) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 18.57k. Recommended Rprot value is10k.
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Figure1: Waveforms
NORMAL OPERATION INPUT LOAD VOLTAGE STATUS UNDERVOLTAGE VCC
VUSD VUSDhyst
INPUT LOAD VOLTAGE STATUS
undefined
OVERVOLTAGE VCC INPUT LOAD VOLTAGE STATUS OPENLOAD INPUT LOAD VOLTAGE STATUS
tDOL(on) tDOL(on) VOV VCCVOV VOVhyst
OVERTEMPERATURE ENABLE Tj INPUT LOAD CURRENT STATUS
TTSD TR
SHORT TO VCC INPUT LOAD VOLTAGE STATUS
undefined tDOL(off) undefined tDOL(off)
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VN710SP
PowerSO-10TM MECHANICAL DATA
DIM. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) (*)
(*) Muar only POA P013P
mm. MIN. 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 1.27 1.25 1.20 13.80 13.85 0.50 1.20 0.80 0 2 1.80 1.10 8 8 0.047 0.031 0 2 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 TYP MAX. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 MIN. 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232
inch TYP. MAX. 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 0.050 0.053 0.055 0.567 0.565 0.002 0.070 0.043 8 8
B
0.10 A B
10
H
E
E2
E
E4
1
SEATING PLANE e
0.25
B
DETAIL "A"
A
C D = D1 = = = SEATING PLANE
h
A F A1
A1
L DETAIL "A"
P095A
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VN710SP
PowerSO-10TM SUGGESTED PAD LAYOUT
14.6 - 14.9
B
TUBE SHIPMENT (no suffix)
CASABLANCA MUAR
C
10.8- 11 6.30
A A
C
0.67 - 0.73 1 2 3 4 5 10 9 8 7 6 1.27 0.54 - 0.6
B
9.5
All dimensions are in mm. Base Q.ty Bulk Q.ty Tube length ( 0.5) Casablanca Muar 50 50 1000 1000 532 532 A B C ( 0.1) 0.8 0.8
10.4 16.4 4.9 17.2
TAPE AND REEL SHIPMENT (suffix "13TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 24 1.5 1.5 11.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
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VN710SP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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